The present invention relates to the structure and fabrication of integrated circuits, especially integrated circuits including memory.
As the minimum size for defining features of an integrated circuit (also referred to as the “groundrule”) shrinks from one generation to the next, the tolerances for performing the various processes in fabricating an integrated circuit become tighter. While some features of an integrated circuit can be readily shrunk in proportion to the reduced groundrule, other features cannot. With each reduction in the groundrule, the properties of particular processes and materials limit the ability to construct certain features at reduced sizes.
This challenge particularly impacts the design of dynamic random access memories (DRAMs) and integrated circuits having both logic circuits and embedded DRAMs. DRAMs are generally designed to the smallest groundrule, in order to provide maximum data storage capacity within very small integrated circuit area. The structure of a conventional DRAM 10 is illustrated in top-down (plan) view in FIG. 1. The DRAM includes a memory cell array 12 having memory cells each including a transistor formed in a semiconductor substrate and a storage capacitor (not shown in FIG. 1). As used herein, the term “horizontal” means in a direction parallel to the major surface of the semiconductor substrate. As shown in FIG. 1, the DRAM 10 includes wordlines (e.g. wordlines W1, W2, . . . Wn) which run in a first horizontal direction over a memory array 12. The wordlines typically include conductor portions including polysilicon and/or a metal and/or a metal silicide. The wordline typically is encapsulated with an insulator, i.e. having an insulating cap above the conductor and insulating spacers formed on sidewalls of the conductor. Bitlines, e.g. bitlines B1, . . . Bn, run over the memory array 12 in a second horizontal direction transverse to the wordlines.
Transistors of the memory cell array are operated by the wordlines. The transistors of a row of memory cells are turned on by a certain wordline. Pairs of bitlines then carry signals representative of data bits between the memory cells of which the transistors are turned on and sense amplifiers 140 through 142. As shown in FIG. 1, the pairs of bitlines are connected to sense amplifiers which alternate between a first external region 14 which is disposed near a first edge of the memory array 12 and a second external region 16 which is disposed near a second edge of the memory array 12. For example, a pair of bitlines B1, B2 carry signals between a pair of memory cells and a sense amplifier 140 located in region 14. A pair of bitlines B3, B4 carry signals between a pair of memory cells and a sense amplifier 141 located in region 16. A pair of bitlines Bn-1, Bn carry signals between a pair of memory cells and a sense amplifier 142 located in region 14.
Bitlines are connected to each memory cell through a contact 18 to the substrate. The bitline contact 18 is a vertically oriented conductive structure that contacts a transistor drain region formed in the substrate. The bitline is formed through an opening between two adjacent wordlines, e.g W1, and W2. Typically, the bitline contacts 18 are formed in a borderless manner to the wordlines by etching selective to the material of the insulating cap and spacers and depositing polysilicon and/or a metal silicide to fill the resultant opening.
Conventionally, bitlines and bitline contacts in advanced DRAMs are formed by two patterning processes. A critical dimension mask is used to define patterns for forming the bitline contacts in the array region 12. The patterns produced by the first patterning process can include only via patterns or they can be line-space patterns. Heavily doped polysilicon or other suitable conductor is deposited in the via patterns and/or line patterns to form the bitline contacts between encapsulated wordlines. If line patterns are formed in the first process, a linearly extending lower layer of polysilicon may also be formed on the bitline contacts as a lower layer of the bitlines. Thereafter, an interlevel dielectric layer is deposited.
Conventionally, to form the second pattern level, a second critical dimension mask is used to define the locations for forming first level horizontally oriented conductive lines in both the memory array region 12 and in the external regions 14 and 16 outside of the memory array region 12. In the memory array region, these conductive lines are formed either as bitlines or as upper metal layers of bitlines. Patterning the conductive lines of the external regions and the memory cell array area with the same mask ensures that the conductive lines interconnect the memory array region to the external regions.
However, it is not possible with normal techniques to fabricate the second patterns by the second critical dimension mask in perfect alignment with the lower level bitline contact patterns and/or lower bitline layer patterns that are formed by the first critical dimension mask. As the groundrule is reduced from one technology generation to the next, this problem worsens. FIG. 1B is a top-down view illustrating the overlay of the metal patterns 20 in the array area 12 relative to the bitline contacts 18 and/or lower bitline layer 22. When the groundrule is very small, e.g. in the neighborhood of 100 nm and smaller, it becomes impossible to overlay the metal patterns 20 in alignment with the bitline contacts 18. As shown in FIG. 1B, the metal patterns 20 are somewhat misaligned with the bitline contacts 18 and lower bitline layer 22. This results in small spacing 24 between bitline contact (CB) 18 and the metal pattern 20. As the groundrule is decreased, potential misalignment increases, such that the spacing 24 decreases to the point where the metal pattern 20 for a bitline, e.g. bitline B2, touches the bitline contacts 18 and/or lower bitline layer 22 of a neighboring bitline such as bitline B1. Such misalignment results in complete failure of the memory array region, requiring the integrated circuit to be discarded. Misalignment to smaller degrees can degrade the devices by introducing higher contact resistivities.
FIG. 2 illustrates worst case overlay results between bitline contacts (CB) and the first level metal patterns (M0) which form the upper layer of bitlines, as formed according to the conventional process described above. FIG. 2 illustrates the worst cases which result when the processes used to form the bitline contacts and the first level metal patterns are performed under worst conditions within processing tolerances. In FIG. 2, the positive numbers on the vertical axis represent the spacing which separates a particular CB pattern from an M0 pattern that are out of alignment. Ideally, each CB pattern should line up perfectly with the same M0 pattern. Misalignment results in these patterns failing to line up. Negative numbers indicate overlap between a CB pattern and the adjacent M0 pattern. The horizontal axis is in the direction of decreasing minimum feature size, i.e. the groundrule. The data points indicated by circular markers are for processing without etch bias. The data points indicated by triangular markers are for processing when etch bias is used. As indicated in FIG. 2, under worst case processing conditions, the CB pattern and the adjacent M0 pattern begin to overlap when the groundrule is decreased below about 150 nm. For example, when the groundrule is 100 nm, the overlap between CB and adjacent M0 is potentially up to about 30 nm when no etch bias is applied and potentially as high as 50 nm when etch bias is applied.
Therefore, it is apparent that the prior art methods result in overlay error between bitline contacts and/or a lower bitline layer formed by a first critical dimension mask and the metal patterns formed by a separate critical dimension mask. As the groundrule is decreased, such overlay error has a greater and more destructive impact on processing.
Accordingly, it would be desirable to eliminate the overlay error between bitline contact patterns and/or lower layer bitline patterns and metal layer bitline patterns that are formed thereon.
It would further be desirable to provide a process for defining metal layer bitline patterns by the same critical dimension mask that is used to form the bitline contacts and/or lower layer bitline patterns.
It would further be desirable to provide a process for defining first level horizontal metal lines of the external regions by a second critical dimension mask that is different from that used to define the metal layer bitline patterns of the memory array region.
In addition, it would be desirable to provide a process by which improved interconnections are formed between the bitlines of a memory array region and regions external to the memory array.